This invention relates generally to level shifter circuitry and more particularly, it relates to an improved level shifter circuit for use with an extremely low power supply voltage.
As is generally well-known, digital logic circuits are widely used in the areas of electronics and computer-type equipment. However, the various digital logic circuits that must communicate with one another may have different power supply voltages. For example, a first circuit that operates with logic levels between 0 V (L) and 2.0 V (H) may need to communicate with a second circuit that operates with logic levels between 0 V (L) and 3.3 V (H). Thus, when a first digital logic circuit of one power supply voltage is required to interface with a second digital logic circuit of another power supply voltage there is typically needed a voltage conversion or translation between the two different power supplies so that they will be compatible with each other and not drain static current. A level shifter circuit is provided to perform this function.
In FIG. 1, there is shown a schematic circuit diagram of a prior art level shifter circuit 10 which may be used to perform a voltage conversion. The level shifter circuit 10 is comprised of a pass N-channel MOS transistor N1; pull-up P-channel MOS transistors P1, P2; and pull-down N-channel MOS transistors N4, N5. The first P-channel transistor P1 has its source connected to the source of the second P-channel transistor P2 and to a high voltage HV, which is typically at approximately VCC-+10 volts The drain of the transistor P1 is connected to the gate of the transistor P2 and to the source of the pass transistor N1. The gate of the transistor P1 is connected to the drain of the transistor P2 at a node A, which is connected to an output terminal OUT.
The pass transistor N1 has its drain connected to an input terminal IN for receiving an input signal and to the gate of the pull-down transistor N5. The gate of the transistor N1 is connected to a first power supply potential VCC, which is typically at +2.0 V. The pull-down transistor N4 has its drain connected also to the node A and to the output terminal OUT. The pull-down transistor N5 has its drain connected to the source of the transistor N4 and its source connected to a second power supply or ground potential VSS (zero volts). The n-type substrate of the P-channel transistors P1, P2 is tied to its source and to the high voltage NV.
In operation, when the input signal at the input terminal IN is at 0 volts the pull-up transistor P2 will be turned ON and the transistors P1 and N5 will both be turned OFF. As a result, the level shifter circuit 10 will produce a voltage level of HV (i.e., +9 V) at the output terminal OUT. On the other hand, when the input signal at the input terminal IN is at VCC (i.e., 2.0 V), the transistors N5 and P1 will both be turned ON and the transistor P2 will be turned OFF. Thus, the level shifter circuit 10 will provide a voltage level of 0 volts at the output terminal OUT.
However, this existing prior art level shifter circuit 10 suffers from the principal disadvantage that it will fail or not operate when the power supply voltage VCC is reduced down to an extremely low voltage, such as +1.0 volts which is equivalent to the threshold voltage of the P-channel MOS transistors P1, P2 and HV=VCC. In view of the trend for deep-submicron CMOS technology, lower and lower power supply voltages VCC are being used. Thus, as the power supply voltage VCC is made lower to be near or below the threshold voltage of the P-channel transistors P1, P2 and the high voltage HV is made to be equal to the supply potential VCC, neither of the pull-up transistors P1 or P2 will be able to be turned ON and consequently, the node A or output terminal OUT will be left floating.
Further, as the thickness of the gate oxides for forming the CMOS transistors are being made thinner and thinner in the CMOS technology, such as 60 .ANG. (angstrom) or below, a voltage difference higher than about +2.4 V-+2.5 V applied across the gate and the bulk of the transistor device will cause a breakdown in the gate oxide to occur, thereby creating a failure. For example, when the input signal of 0 volts is applied to the gate of the transistor P2 in FIG. 1, the level shifter circuit 10 will generate a voltage level of HV volts at the output terminal OUT. As will, be noted, there will be created a voltage difference of HV between the drains and the gates of the P-channel transistors P1, P2. If the transistors P1, P2 were made of thin oxide; this will cause a breakdown of the thinner gate oxides.
Therefore, it would be desirable to provide an improved level shifter circuit which is designed to be capable of operating with an extremely low power supply voltage. Further, it would be expedient that the level shifter circuit be able to prevent the breakdown of the gate oxide in all of the transistors.